Phase-locked loop (PLL) circuits are widely used to provide clocks for operations of circuit blocks. PLL circuits are used in a variety of modern electronic systems including communication systems, multimedia systems and various other applications such as frequency synthesizers, FM demodulators, clock recovery circuits and tone decoders.
FIG. 1 is a block diagram illustrating a conventional phase-locked-loop circuit. Referring to FIG. 1, the PLL circuit 100 includes a phase/frequency detector (PFD) 110, a charge pump 130, a loop filter 140, a voltage-controlled oscillator (VCO) 150, a frequency divider 160, and a fractional frequency divider 165. The PFD 110 generates an up signal UP and a down signal DN based on a phase difference and a frequency difference between an input signal SIN and a feedback signal SFEED. The charge pump 130 generates a charge current and a discharge current, based on the up signal UP and the down signal DN. The loop filter 140 integrates the charge current and the discharge current to generate an oscillation control voltage VCON. The loop filter 140 may include a capacitor, which is electrically coupled between the charge pump 130 and the VCO 150. Therefore, the oscillation control voltage VCON is determined according to an integrated value of the output current IOUT. The VCO 150 generates an oscillation output signal SOUT of which a frequency varies according to a magnitude of the oscillation control voltage VCON. The frequency divider 160 divides a frequency of the oscillation output signal SOUT by an integer. The fractional frequency divider 165 may include a delta-sigma modulator, and divide the frequency of the oscillation output signal SOUT by a fractional number.
When there is a mismatch between an up current and a down current of the charge pump, the performance of the PLL circuit 100 may be degraded. The up current is a current that charges the loop filter, and the down current is a current that discharges the loop filter. When the PLL circuit 100 is in a locked state, the oscillation control voltage VCON is expected to have a constant value. However, when a mismatch is generated between the up current and the down current of the charge pump, the oscillation control voltage VCON may include a ripple even when the PLL circuit 100 is in the locked state. When the oscillation control voltage VCON has a ripple, the output signal of the PLL circuit 100 may include a jitter and a reference spur having large value.
In particular, in the PLL circuit having a fractional frequency divider, the performance of the PLL circuit may be further degraded when there is a mismatch between an up current and a down current of the charge pump. When there is a mismatch between an up current and a down current of the charge pump, the noise generated in the delta-sigma modulator and the in-band noise of the PLL circuit may be increased, and the output signal of the PLL circuit may include a jitter having large value.
The mismatch between the up current and the down current of the charge pump may be decreased by adjusting the size of a PMOS transistor and an NMOS transistor constituting the charge pump. However, there is a limit related to variations in manufacturing processes and variations of the oscillation control voltage that decrease the mismatch between the up current and the down current of the charge pump.